On Threshold Voltage Variation-Tolerant Designs

Abstract

Scaling CMOS transistors has been used to achieve smaller, faster, and cheaper integrated circuits. However,
with CMOS transistors moving deep towards the nanometer range, the eects threshold voltage (VTH) variations
(besides other variations and noises) play on their reliabilities and that of the gates they are forming are worrying.
For mitigating against this trend, sizing can be used to improve on the reliability of the CMOS gates. Simultaneously,
sizing can also reduce power or maintain speed while only marginally aecting area. For evaluating the advantages
sizing still holds, inverters of dierent sizings are compared in this paper with reliability enhanced inverters using
well-known redundancy schemes like triple modular redundancy and hammock networks. Simulation results show
that, at the same reliability, sizing can lead to designs outperforming those obtained by the other methods on any of the
design parameters (i.e., area, power or delay). These are reinforcing previous reports showing that space redundancy
applied at the device-level outperform gate-level solutions.